/* SPDX-License-Identifier: GPL-2.0+ */

#ifndef _SDHCI_REG_H
#define _SDHCI_REG_H
#include "cv186x_reg.h"

#define CVI_SDHCI_VENDOR_OFFSET 0x200
#define CVI_SDHCI_PHY_TX_RX_DLY	(CVI_SDHCI_VENDOR_OFFSET + 0x40)
#define CVI_SDHCI_PHY_DS_DLY	(CVI_SDHCI_VENDOR_OFFSET + 0x44)
#define CVI_SDHCI_PHY_DLY_STS	(CVI_SDHCI_VENDOR_OFFSET + 0x48)
#define CVI_SDHCI_PHY_CONFIG	(CVI_SDHCI_VENDOR_OFFSET + 0x4C)

#define CVI_SDHCI_BIT_CLK_FREE_EN 2
#define CVI_SDHCI_CLK_FREE_EN_VALUE 0
#define CVI_SDHCI_CLK_FREE_EN_MASK 0xFFFFFFFB
#define CVI_SDHCI_VENDOR_MSHC_CTRL_R (CVI_SDHCI_VENDOR_OFFSET + 0x0)
#define CVI_SDHCI_PHY_RX_DLY_SHIFT 16
// Bit 16~22
#define CVI_SDHCI_PHY_RX_DLY_MASK 0x7F0000
#define CVI_SDHCI_PHY_TX_RX_DLY (CVI_SDHCI_VENDOR_OFFSET + 0x40)
#define CVI_SDHCI_PHY_RX_SRC_BIT_1 24
#define CVI_SDHCI_PHY_RX_SRC_BIT_2 25

#define SDHCI_PHY_CONFIG                                                       \
	(CVI_SDHCI_VENDOR_OFFSET +                                             \
	 0x4C) // P_VERDOR_SPECIFIC_AREA + 0x4c0x24c( PHY_TX_BPS )
#define REG_TX_BPS_SEL_MASK 0xFFFFFFFE
#define REG_TX_BPS_SEL_CLR_MASK (0x1) // 0x24c  PHY_TX_BPS
#define REG_TX_BPS_SEL_SHIFT (0) // 0x24c  PHY_TX_BPS
#define REG_TX_BPS_SEL_BYPASS (1) // 0x24c PHY_TX_BPS inv

#define MMC_MAX_CLOCK (375000000)
#define MMC_MAX_CLOCK_DIV_VALUE (0x40009)

#define MAX_TUNING_CMD_RETRY_COUNT 50
#define TUNE_MAX_PHCODE	128
#define TAP_WINDOW_THLD 20
#endif
